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2669 motorola smallsignal transistors, fets and diodes device data npn silicon maximum ratings rating symbol value unit collector emitter voltage v ceo 25 vdc collector base voltage v cbo 30 vdc emitter base voltage v ebo 3.0 vdc total device dissipation @ t a = 25 c derate above 25 c p d 350 2.8 mw mw/ c total device dissipation @ t c = 25 c derate above 25 c p d 1.0 8.0 watts mw/ c operating and storage junction temperature range t j , t stg 55 to +150 c thermal characteristics characteristic symbol max unit thermal resistance, junction to ambient r ja 357 c/w thermal resistance, junction to case r jc 125 c/w electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics collector emitter breakdown voltage (i c = 1.0 madc, i b = 0) v (br)ceo 25 e vdc collector base breakdown voltage (i c = 100 adc, i e = 0) v (br)cbo 30 e vdc emitter base breakdown voltage (i e = 10 adc, i c = 0) v (br)ebo 3.0 e vdc collector cutoff current (v cb = 25 vdc, i e = 0) i cbo e 100 nadc emitter cutoff current (v eb = 2.0 vdc, i c = 0) i ebo e 100 nadc preferred devices are motorola recommended choices for future use and best overall value.

semiconductor technical data motorola preferred devices case 2904, style 2 to92 (to226aa) 1 2 3 collector 3 1 base 2 emitter
2670 motorola smallsignal transistors, fets and diodes device data electrical characteristics (t a = 25 c unless otherwise noted) (continued) characteristic symbol min max unit on characteristics dc current gain (i c = 4.0 madc, v ce = 10 vdc) h fe 60 e e collector emitter saturation voltage (i c = 4.0 madc, i b = 0.4 madc) v ce(sat) e 0.5 vdc base emitter on voltage (i c = 4.0 madc, v ce = 10 vdc) v be(on) e 0.95 vdc small signal characteristics current gain e bandwidth product (i c = 4.0 madc, v ce = 10 vdc, f = 100 mhz) f t 650 e mhz collectorbase capacitance (v cb = 10 vdc, i e = 0, f = 1.0 mhz) c cb e 0.7 pf commonbase feedback capacitance (v cb = 10 vdc, i e = 0, f = 1.0 mhz) mpsh10 mpsh11 c rb 0.35 0.6 0.65 0.9 pf collector base time constant (i c = 4.0 madc, v cb = 10 vdc, f = 31.8 mhz) rb'c c e 9.0 ps
22 motorola smallsignal transistors, fets and diodes device data embossed tape and reel sot-23, sc-59, sc-70/sot-323, sc90/sot416, sot-223 and so-16 packages are available only in tape and reel. use the appropriate suffix indicated below to order any of the sot-23, sc-59, sc-70/sot-323, sot-223 and so-16 packages. (see section 6 on packaging for additional information). sot-23: available in 8 mm tape and reel use the device title (which already includes the at1o suffix) to order the 7 inch/3000 unit reel. replace the at1o suffix in the device title with a at3o suffix to order the 13 inch/10,000 unit reel. sc-59: available in 8 mm tape and reel use the device title (which already includes the at1o suffix) to order the 7 inch/3000 unit reel. replace the at1o suffix in the device title with a at3o suffix to order the 13 inch/10,000 unit reel. sc-70/ available in 8 mm tape and reel sot-323: use the device title (which already includes the at1o suffix) to order the 7 inch/3000 unit reel. replace the at1o suffix in the device title with a at3o suffix to order the 13 inch/10,000 unit reel. sot-223: available in 12 mm tape and reel use the device title (which already includes the at1o suffix) to order the 7 inch/1000 unit reel. replace the at1o suffix in the device title with a at3o suffix to order the 13 inch/4000 unit reel. so-16: available in 16 mm tape and reel add an ar1o suffix to the device title to order the 7 inch/500 unit reel. add an ar2o suffix to the device title to order the 13 inch/2500 unit reel. radial tape in fan fold box or reel to-92 packages are available in both bulk shipments and in radial tape in fan fold boxes or reels. fan fold boxes and radial tape reel are the best methods for capturing devices for automatic insertion in printed circuit boards. to-92: available in fan fold box add an arlro suffix and the appropriate style code* to the device title to order the fan fold box. available in 365 mm radial tape reel add an arlro suffix and the appropriate style code* to the device title to order the radial tape reel. *refer to section 6 on packaging for style code characters and additional information on ordering * requirements. device markings/date code characters sot-23, sc-59, sc-70/sot-323, and the sc90/sot416 packages have a device marking and a date code etched on the device. the generic example below depicts both the device marking and a representa- tion of the date code that appears on the sc-70/sot-323, sc-59 and sot-23 packages. abc d the ado represents a smaller alpha digit date code. the date code indicates the actual month in which the part was manufactured.
tape and reel specifications 62 motorola smallsignal transistors, fets and diodes device data tape and reel specifications and packaging specifications embossed tape and reel is used to facilitate automatic pick and place equipment feed requirements. the tape is used as the shipping container for various products and requires a minimum of handling. the antistatic/conductive tape provides a secure cavity for the product when sealed with the apeelbacko cover tape. w two reel sizes available (7 , and 13 , ) w used for automatic pick and place feed systems w minimizes product handling w eia 481, 1, 2 w sod123, sc59, sc70/sot323, sc70ml/sot363, sot23, tsop6, in 8 mm tape w sot223 in 12 mm tape w so14, so16 in 16 mm tape use the standard device title and add the required suffix as listed in the option table on the following page. note that the in dividual reels have a finite number of devices depending on the type of product contained in the tape. also note the minimum lot size is one full reel for each line item, and orders are required to be in increments of the single reel quantity. of feed direction sc59, sc70/sot323, sot23 8 mm 8 mm 12 mm sot223 sod123 16 mm so14, 16 sc70ml/sot363, tsop6 t1 orientation 8 mm sc70ml/sot363 t2 orientation 8 mm embossed tape and reel ordering information package tape width (mm) pitch mm (inch) reel size mm (inch) devices per reel and minimum order quantity device suffix sc59 8 4.0 + 0.1 (.157 + .004) 178 (7) 3,000 t1 sc70/sot323 8 4.0 + 0.1 (.157 + .004) 178 (7) 3,000 t1 8 330 (13) 10,000 t3 so14 16 8.0 + 0.1 (.315 + .004) 178 (7) 500 r1 16 330 (13) 2,500 r2 so16 16 8.0 + 0.1 (.315 + .004) 178 (7) 500 r1 16 330 (13) 2,500 r2 sod123 8 4.0 + 0.1 (.157 + .004) 178 (7) 3,000 t1 8 330 (13) 10,000 t3 sot23 8 4.0 + 0.1 (.157 + .004) 178 (7) 3,000 t1 8 330 (13) 10,000 t3 sot223 12 8.0 + 0.1 (.315 + .004) 178 (7) 1,000 t1 12 330 (13) 4,000 t3 sc70ml/sot363 8 4.0 + 0.1 (.157 + .004) 178 (7) 3,000 t1 8 178 (7) 3,000 t2 tsop6 8 4.0 + 0.1 (.157 + .004) 178 (7) 3,000 t1
63 tape and reel specifications motorola smallsignal transistors, fets and diodes device data embossed tape and reel data for discretes carrier tape specifications p 0 k t b 1 k 0 top cover tape embossment user direction of feed center lines of cavity d p 2 10 pitches cumulative tolerance on tape + 0.2 mm ( + 0.008 , ) e f w p b 0 a 0 d 1 for components 2.0 mm x 1.2 mm and larger * top cover tape thickness (t 1 ) 0.10 mm (.004 , ) max. embossment embossed carrier r min bending radius maximum component rotation typical component cavity center line typical component center line 100 mm (3.937 , ) 250 mm (9.843 , ) 1 mm (.039 , ) max 1 mm max 10 5 tape and components shall pass around radius aro without damage tape for machine reference only including draft and radii concentric around b 0 camber (top view) allowable camber to be 1 mm/100 mm nonaccumulative over 250 mm see note 1 bar code label dimensions tape size b 1 max d d 1 e f k p 0 p 2 r min t max w max 8mm 4.55 mm (.179 , ) 1 .5 +0 . 1mm 0.0 ( 0 9 + 004 1.0 min (.039 , ) 1 . 7 5 + 0 . 1mm (.069 + .004 , ) 3.5 + 0.05 mm (.138 + .002 , ) 2.4 mm max (.094 , ) 4 . 0 + 0 . 1mm (.157 + .004 , ) 2 . 0 + 0 . 1mm (.079 + .002 , ) 25 mm (.98 , ) 0 . 6mm (.024 , ) 8.3 mm (.327 , ) 12 mm 8.2 mm (.323 , ) ( . 0 5 9+ . 004 , 0.0) 1 .5 mm mi n (.060 , ) 5.5 + 0.05 mm (.217 + .002 , ) 6.4 mm max (.252 , ) 30 mm (1.18 , ) 12 + .30 mm (.470 + .012 , ) 16 mm 12.1 mm (.476 , ) 7.5 + 0.10 mm (.295 + .004 , ) 7.9 mm max (.311 , ) 16.3 mm (.642 , ) 24 mm 20.1 mm (.791 , ) 11.5 + 0.1 mm (.453 + .004 , ) 11.9 mm max (.468 , ) 24.3 mm (.957 , ) metric dimensions govern e english are in parentheses for reference only. note 1: a 0 , b 0 , and k 0 are determined by component size. the clearance between the components and the cavity must be within .05 mm min. to .50 mm max ., note 1: the component cannot rotate more than 10 5 within the determined cavity. note 2: if b 1 exceeds 4.2 mm (.165) for 8 mm embossed tape, the tape may not feed through all tape feeders. note 3: pitch information is contained in the embossed tape and reel ordering information on pg. 5.123.
tape and reel specifications 64 motorola smallsignal transistors, fets and diodes device data embossed tape and reel data for discretes a full radius t max g 20.2 mm min (.795 , ) 1.5 mm min (.06 , ) 13.0 mm + 0.5 mm (.512 , + .002 , ) 50 mm min (1.969 , ) outside dimension measured at edge inside dimension measured near hub size a max g t max 8 mm 330 mm (12.992 , ) 8.4 mm + 1.5 mm, 0.0 (.33 , + .059 , , 0.00) 14.4 mm (.56 , ) 12 mm 330 mm (12.992 , ) 12.4 mm + 2.0 mm, 0.0 (.49 , + .079 , , 0.00) 18.4 mm (.72 , ) 16 mm 360 mm (14.173 , ) 16.4 mm + 2.0 mm, 0.0 (.646 , + .078 , , 0.00) 22.4 mm (.882 , ) 24 mm 360 mm (14.173 , ) 24.4 mm + 2.0 mm, 0.0 (.961 , + .070 , , 0.00) 30.4 mm (1.197 , ) reel dimensions metric dimensions govern e english are in parentheses for reference only
65 packaging specifications motorola smallsignal transistors, fets and diodes device data to92 eia, iec, eiaj radial tape in fan fold box or on reel radial tape in fan fold box or on reel of the reliable to92 package are the best methods of capturing devices for automatic insertion in printed circuit boards. these methods of taping are compatible with various equipment for active and passive component insertion. w available in fan fold box w available on 365 mm reels w accommodates all standard inserters w allows flexible circuit board layout w 2.5 mm pin spacing for soldering w eia468, iec 2862, eiaj rc1008b ordering notes: when ordering radial tape in fan fold box or on reel, specify the style per figures 3 through 8. add the suffix arlro and astyleo to the device title, i.e. mps3904rlra. this will be a standard mps3904 radial taped and supplied on a reel per figure 9. fan fold box information e order in increments of 2000. reel information e order in increments of 2000. us/european suffix conversions us europe rlra rl rlre rl1 rlrm zl1 to92 radial tape in fan fold box or on reel
packaging specifications 66 motorola smallsignal transistors, fets and diodes device data to92 eia radial tape in fan fold box or on reel h2a h2a h f1 f2 p2 p2 p1 p d w w1 l1 w2 h2b h2b t1 t t2 h4 h5 h1 figure 1. device positioning on tape l specification inches millimeter symbol item min max min max d tape feedhole diameter 0.1496 0.1653 3.8 4.2 d2 component lead thickness dimension 0.015 0.020 0.38 0.51 f1, f2 component lead pitch 0.0945 0.110 2.4 2.8 h bottom of component to seating plane .059 .156 1.5 4.0 h1 feedhole location 0.3346 0.3741 8.5 9.5 h2a deflection left or right 0 0.039 0 1.0 h2b deflection front or rear 0 0.051 0 1.0 h4 feedhole to bottom of component 0.7086 0.768 18 19.5 h5 feedhole to seating plane 0.610 0.649 15.5 16.5 l defective unit clipped dimension 0.3346 0.433 8.5 11 l1 lead wire enclosure 0.09842 e 2.5 e p feedhole pitch 0.4921 0.5079 12.5 12.9 p1 feedhole center to center lead 0.2342 0.2658 5.95 6.75 p2 first lead spacing dimension 0.1397 0.1556 3.55 3.95 t adhesive tape thickness 0.06 0.08 0.15 0.20 t1 overall taped package thickness e 0.0567 e 1.44 t2 carrier strip thickness 0.014 0.027 0.35 0.65 w carrier strip width 0.6889 0.7481 17.5 19 w1 adhesive tape width 0.2165 0.2841 5.5 6.3 w2 adhesive tape position .0059 0.01968 .15 0.5 notes: 1. maximum alignment deviation between leads not to be greater than 0.2 mm. 2. defective components shall be clipped from the carrier tape such that the remaining protrusion (l) does not exceed a maximum of 11 mm. 3. component lead to tape adhesion must meet the pull test requirements established in figures 5, 6 and 7. 4. maximum noncumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches. 5. holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive. 6. no more than 1 consecutive missing component is permitted. 7. a tape trailer and leader, having at least three feed holes is required before the first and after the last component. 8. splices will not interfere with the sprocket feed holes.
67 packaging specifications motorola smallsignal transistors, fets and diodes device data to92 eia radial tape in fan fold box or on reel ??????? ??????? ??????? ??????? adhesive tape on top side flat side carrier strip flat side of transistor and adhesive tape visible. adhesive tape on top side rounded side carrier strip rounded side of transistor and adhesive tape visible. 252 mm 9.92o 58 mm 2.28o max max 13o max 330 mm style m fan fold box is equivalent to styles e and f of reel pack dependent on feed orientation from box. style p fan fold box is equivalent to styles a and b of reel pack dependent on feed orientation from box. 100 gram pull force 16 mm holding fixture holding fixture holding fixture 16 mm 70 gram pull force 500 gram pull force the component shall not pull free with a 300 gram load applied to the leads for 3 + 1 second. the component shall not pull free with a 70 gram load applied to the leads for 3 + 1 second. there shall be no deviation in the leads and no component leads shall be pulled free of the tape with a 500 gram load applied to the component body for 3 + 1 second. figure 2. style m figure 3. style p figure 4. fan fold box dimensions figure 5. test #1 figure 6. test #2 figure 7. test #3 adhesion pull tests fan fold box styles
packaging specifications 68 motorola smallsignal transistors, fets and diodes device data to92 eia radial tape in fan fold box or on reel reel styles arbor hole dia. 30.5mm + 0.25mm marking note recess depth 9.5mm min 48 mm max core dia. 82mm + 1mm hub recess 76.2mm + 1mm 365mm + 3, 0mm 38.1mm + 1mm material used must not cause deterioration of components or degrade lead solderability carrier strip adhesive tape rounded side feed rounded side of transistor and adhesive tape visible. adhesive tape on reverse side carrier strip flat side feed flat side of transistor and carrier strip visible (adhesive tape on reverse side). carrier strip adhesive tape flat side feed flat side of transistor and adhesive tape visible. rounded side of transistor and carrier strip visible (adhesive tape on reverse side). feed adhesive tape on reverse side carrier strip rounded side figure 8. reel specifications figure 9. style a figure 10. style b figure 11. style e figure 12. style f
surface mount information 710 motorola smallsignal transistors, fets and diodes device data information for using surface mount packages recommended footprints for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection inter- face between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. power dissipation for a surface mount device the power dissipation for a surface mount device is a func- tion of the drain/collector pad size. these can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device. for example, for a sot223 device, p d is calculated as follows. p d = 150 c 25 c 156 c/w = 800 milliwatts the 156 c/w for the sot223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 800 milliwatts. there are other alternatives to achieving higher power dissipation from the surface mount packages. one is to increase the area of the drain/collector pad. by increasing the area of the drain/collector pad, the power dissipation can be increased. although the power dissipation can almost be doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. for example, a graph of r q ja versus drain pad area is shown in figure 1. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. to ambient ( c/w) r ja , thermal re s i s tance , j u ncti o n q 0.8 watts 1.25 watts* 1.5 watts a, area (square inches) 0.0 0.2 0.4 0.6 0.8 1.0 160 140 120 100 80 board material = 0.0625 g10/fr4, 2 oz copper t a = 25 c *mounted on the dpak footprint figure 1. thermal resistance versus drain pad area for the sot223 package (typical) solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sot23, sc59, sc70/sot323, sc90/sot416, sod123, sot223, sot363, so14, so16, and tsop6 packages, the stencil opening should be the same as the pad size or a 1:1 registration.
711 surface mount information motorola smallsignal transistors, fets and diodes device data soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to mini- mize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference should be a maximum of 10 c. ? the soldering temperature and time should not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used since the use of forced cooling will increase the temperature gradient and will result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remem- bers these profiles from one operating session to the next. figure 2 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 170 c 140 c figure 2. typical solder heating profile desired curve for high mass assemblies
surface mount information 712 motorola smallsignal transistors, fets and diodes device data footprints for soldering 0.094 2.4 sc59 mm inches 0.037 0.95 0.037 0.95 0.039 1.0 0.031 0.8 sot23 mm inches 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 so14, so16 mm inches 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 sot223 0.079 2.0 0.15 3.8 0.248 6.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 0.091 2.3 0.091 2.3 mm inches mm inches 0.035 0.9 0.075 0.7 1.9 0.028 0.65 0.025 0.65 0.025 sc70/sot323 1.4 1 0.5 min. (3x) 0.5 min. (3x) 0.5 sot 416/sc90
713 surface mount information motorola smallsignal transistors, fets and diodes device data sot363 (sc70 6 lead) 0.5 mm (min) 0.4 mm (min) 0.65 mm 0.65 mm 1.9 mm sod123 mm inches 0.91 0.036 1.22 0.048 2.36 0.093 4.19 0.165 inches mm 0.028 0.7 0.074 1.9 0.037 0.95 0.037 0.95 0.094 2.4 0.039 1.0 tsop6
package outline dimensions 82 motorola smallsignal transistors, fets and diodes device data package outline dimensions dimensions are in inches unless otherwise noted. notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. contour of package beyond dimension r is uncontrolled. 4. dimension f applies between p and l. dimension d and j apply between l and k minimum. lead dimension is uncontrolled in p and beyond dimension k minimum. r a p j l f b k g h section xx c v d n n xx seating plane dim min max min max millimeters inches a 0.175 0.205 4.45 5.20 b 0.170 0.210 4.32 5.33 c 0.125 0.165 3.18 4.19 d 0.016 0.022 0.41 0.55 f 0.016 0.019 0.41 0.48 g 0.045 0.055 1.15 1.39 h 0.095 0.105 2.42 2.66 j 0.015 0.020 0.39 0.50 k 0.500 12.70 l 0.250 6.35 n 0.080 0.105 2.04 2.66 p 0.100 2.54 r 0.115 2.93 v 0.135 3.43 1 case 02904 (to226aa) to92 plastic style 21: pin 1. collector 2. emitter 3. base style 22: pin 1. source 2. gate 3. drain style 14: pin 1. emitter 2. collector 3. base style 30: pin 1. drain 2. gate 3. source style 1: pin 1. emitter 2. base 3. collector style 2: pin 1. base 2. emitter 3. collector style 3: pin 1. anode 2. anode 3. cathode style 5: pin 1. drain 2. source 3. gate style 7: pin 1. source 2. drain 3. gate style 15: pin 1. anode 1 2. cathode 3. anode 2 style 17: pin 1. collector 2. base 3. emitter style 4: pin 1. cathode 2. cathode 3. anode notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. contour of package beyond dimension r is uncontrolled. 4. dimension f applies between p and l. dimensions d and j apply between l and k mimimum. lead dimension is uncontrolled in p and beyond dimension k minimum. r a p l f b k g h c v n n xx seating plane 1 j section xx d dim min max min max millimeters inches a 0.175 0.205 4.44 5.21 b 0.290 0.310 7.37 7.87 c 0.125 0.165 3.18 4.19 d 0.018 0.022 0.46 0.56 f 0.016 0.019 0.41 0.48 g 0.045 0.055 1.15 1.39 h 0.095 0.105 2.42 2.66 j 0.018 0.024 0.46 0.61 k 0.500 12.70 l 0.250 6.35 n 0.080 0.105 2.04 2.66 p 0.100 2.54 r 0.135 3.43 v 0.135 3.43 23 case 02905 (to226ae) to92 1watt plastic style 1: pin 1. emitter 2. base 3. collector style 14: pin 1. emitter 2. collector 3. base style 22: pin 1. source 2. gate 3. drain
83 package outline dimensions motorola smallsignal transistors, fets and diodes device data package outline dimensions (continued) notes: 1. package contour optional within dia b and length a. heat slugs, if any, shall be included within this cylinder, but shall not be subject to the min limit of dia b. 2. lead dia not controlled in zones f, to allow for flash, lead finish buildup, and minor irregularities other than heat slugs. case 5102 (do204aa) do7 dim min max min max inches millimeters a 5.84 7.62 0.230 0.300 b 2.16 2.72 0.085 0.107 d 0.46 0.56 0.018 0.022 f 1.27 0.050 k 25.40 38.10 1.000 1.500 all jedec dimensions and notes apply. k a d b f k f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. contour of package beyond zone r is uncontrolled. 4. dimension f applies between p and l. dimensions d and j apply between l and k minimum. lead dimension is uncontrolled in p and beyond dim k minimum. case 18202 plastic (t0226ac) to92 a l k b r f p d h g xx seating plane 12 v n c n section xx d j dim min max min max millimeters inches a 0.175 0.205 4.45 5.21 b 0.170 0.210 4.32 5.33 c 0.125 0.165 3.18 4.49 d 0.016 0.022 0.41 0.56 f 0.016 0.019 0.407 0.482 g 0.050 bsc 1.27 bsc h 0.100 bsc 3.54 bsc j 0.014 0.016 0.36 0.41 k 0.500 12.70 l 0.250 6.35 n 0.080 0.105 2.03 2.66 p 0.050 1.27 r 0.115 2.93 v 0.135 3.43 style 1: pin 1. anode 2. cathode
package outline dimensions 84 motorola smallsignal transistors, fets and diodes device data package outline dimensions (continued) case 31808 (to236ab) sot23 d j k l a c b s h g v 3 1 2 dim a min max min max millimeters 0.1102 0.1197 2.80 3.04 inches b 0.0472 0.0551 1.20 1.40 c 0.0350 0.0440 0.89 1.11 d 0.0150 0.0200 0.37 0.50 g 0.0701 0.0807 1.78 2.04 h 0.0005 0.0040 0.013 0.100 j 0.0034 0.0070 0.085 0.177 k 0.0140 0.0285 0.35 0.69 l 0.0350 0.0401 0.89 1.02 s 0.0830 0.1039 2.10 2.64 v 0.0177 0.0236 0.45 0.60 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maxiumum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. style 6: pin 1. base 2. emitter 3. collector style 8: pin 1. anode 2. no connection 3. cathode style 9: pin 1. anode 2. anode 3. cathode style 10: pin 1. drain 2. source 3. gate style 11: pin 1. anode 2. cathode 3. cathodeanode style 12: pin 1. cathode 2. cathode 3. anode style 18: pin 1. no connection 2. cathode 3. anode style 19: pin 1. cathode 2. anode 3. cathodeanode style 21: pin 1. gate 2. source 3. drain plastic s g h d c b l a 1 3 2 j k dim a min max min max inches 2.70 3.10 0.1063 0.1220 millimeters b 1.30 1.70 0.0512 0.0669 c 1.00 1.30 0.0394 0.0511 d 0.35 0.50 0.0138 0.0196 g 1.70 2.10 0.0670 0.0826 h 0.013 0.100 0.0005 0.0040 j 0.09 0.18 0.0034 0.0070 k 0.20 0.60 0.0079 0.0236 l 1.25 1.65 0.0493 0.0649 s 2.50 3.00 0.0985 0.1181 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. case 318d04 sc59 style 3: pin 1. anode 2. anode 3. cathode style 1: pin 1. emitter 2. base 3. collector style 2: pin 1. n.c. 2. anode 3. cathode style 4: pin 1. n.c. 2. cathode 3. anode style 5: pin 1. cathode 2. cathode 3. anode
85 package outline dimensions motorola smallsignal transistors, fets and diodes device data package outline dimensions (continued) h s f a b d g l 4 123 0.08 (0003) c m k j dim a min max min max millimeters 0.249 0.263 6.30 6.70 inches b 0.130 0.145 3.30 3.70 c 0.060 0.068 1.50 1.75 d 0.024 0.035 0.60 0.89 f 0.115 0.126 2.90 3.20 g 0.087 0.094 2.20 2.40 h 0.0008 0.0040 0.020 0.100 j 0.009 0.014 0.24 0.35 k 0.060 0.078 1.50 2.00 l 0.033 0.041 0.85 1.05 m 0 10 0 10 s 0.264 0.287 6.70 7.30 notes: 3. dimensioning and tolerancing per ansi y14.5m, 1982. 4. controlling dimension: inch. case 318e04 sot223 style 1: pin 1. base 2. collector 3. emitter 4. collector style 3: pin 1. gate 2. drain 3. source 4. drain style 2: pin 1. anode 2. cathode 3. nc 4. cathode case 318g02 tsop6 style 1: pin 1. drain 2. drain 3. gate 4. source 5. drain 6. drain 23 4 5 6 a l 1 s g d b h c 0.05 (0.002) dim min max min max inches millimeters a 0.1142 0.1220 2.90 3.10 b 0.0512 0.0669 1.30 1.70 c 0.0354 0.0433 0.90 1.10 d 0.0098 0.0197 0.25 0.50 g 0.0335 0.0413 0.85 1.05 h 0.0005 0.0040 0.013 0.100 j 0.0040 0.0102 0.10 0.26 k 0.0079 0.0236 0.20 0.60 l 0.0493 0.0610 1.25 1.55 m 0 10 0 10 s 0.0985 0.1181 2.50 3.00 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. m j k plastic
package outline dimensions 86 motorola smallsignal transistors, fets and diodes device data package outline dimensions (continued) case 41902 sc70/sot323 c r n a l d g v s b h j k 3 12 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. dim min max min max millimeters inches a 0.071 0.087 1.80 2.20 b 0.045 0.053 1.15 1.35 c 0.035 0.049 0.90 1.25 d 0.012 0.016 0.30 0.40 g 0.047 0.055 1.20 1.40 h 0.000 0.004 0.00 0.10 j 0.004 0.010 0.10 0.25 k 0.017 ref 0.425 ref l 0.026 bsc 0.650 bsc n 0.028 ref 0.700 ref r 0.031 0.039 0.80 1.00 s 0.079 0.087 2.00 2.20 v 0.012 0.016 0.30 0.40 0.05 (0.002) style 3: pin 1. base 2. emitter 3. collector style 4: pin 1. cathode 2. cathode 3. anode style 2: pin 1. anode 2. n.c. 3. cathode style 5: pin 1. anode 2. anode 3. cathode style 7: pin 1. base 2. emitter 3. collector style 9: pin 1. anode 2. cathode 3. cathodeanode style 10: pin 1. cathode 2. anode 3. anodecathode notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. dim a min max min max millimeters 1.80 2.20 0.071 0.087 inches b 1.15 1.35 0.045 0.053 c 0.80 1.10 0.031 0.043 d 0.10 0.30 0.004 0.012 g 0.65 bsc 0.026 bsc h 0.10 0.004 j 0.10 0.25 0.004 0.010 k 0.10 0.30 0.004 0.012 n 0.20 ref 0.008 ref s 2.00 2.20 0.079 0.087 v 0.30 0.40 0.012 0.016 b 0.2 (0.008) mm 123 a g v s h c n j k 654 b d 6 pl case 419b-01 sot363 style 1: pin 1. emitter 2 2. base 2 3. collector 1 4. emitter 1 5. base 1 6. collector 2 style 6: pin 1. anode 2 2. n/c 3. cathode 1 4. anode 1 5. n/c 6. cathode 2
87 package outline dimensions motorola smallsignal transistors, fets and diodes device data package outline dimensions (continued) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 1: pin 1. cathode 2. anode aaa aaa aaa b d k a c e j 1 2 h case 42504 sod123 dim min max min max millimeters inches a 0.055 0.071 1.40 1.80 b 0.100 0.112 2.55 2.85 c 0.037 0.053 0.95 1.35 d 0.020 0.028 0.50 0.70 e 0.004 0.25 h 0.000 0.004 0.00 0.10 j 0.006 0.15 k 0.140 0.152 3.55 3.85 case 46301 sot416/sc90 dim min max min max inches millimeters a 0.70 0.80 0.028 0.031 b 1.40 1.80 0.055 0.071 c 0.60 0.90 0.024 0.035 d 0.15 0.30 0.006 0.012 g 1.00 bsc 0.039 bsc h 0.10 0.004 j 0.10 0.25 0.004 0.010 k 1.45 1.75 0.057 0.069 l 0.10 0.20 0.004 0.008 s 0.50 bsc 0.020 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. m 0.20 (0.008) b a b s d g 3 pl 0.20 (0.008) a k j l c h 3 2 1 style 1: pin 1. base 2. emitter 3. collector style 4: pin 1. cathode 2. cathode 3. anode
package outline dimensions 88 motorola smallsignal transistors, fets and diodes device data package outline dimensions (continued) notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f hg d k c n l j m seating plane dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.300 bsc 7.62 bsc m 0 10 0 10 n 0.015 0.039 0.39 1.01 case 64606 14pin dip plastic notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 case 64808 16pin dip plastic
89 package outline dimensions motorola smallsignal transistors, fets and diodes device data package outline dimensions (continued) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 case 751a03 so14 plastic notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 case 751b05 so16 plastic
reliability and quality assurance 912 motorola smallsignal transistors, fets and diodes device data outgoing quality the average outgoing quality (aoq) refers to the number of devices per million that are outside the specification limits at the time of shipment. motorola has established six sigma goals to improve its outgoing quality and will continue its oerror free performanceo focus to achieve its goal of zero parts per million (ppm) outgoing quality. motorola's present quality level has lead to vendor certification programs with many of its customers. these programs ensure a level of quality which allows the customer either to reduce or eliminate the need for incoming inspections. average outgoing quality (aoq) calculation aoq = (process average) (probability of acceptance) (10 6 ) (ppm) process average = total projected reject devices total number of devices projected reject devices = defects in sample sample size lot size total number of devices = sum of units in each submitted lot probability of acceptance = 1 number of lots rejected number of lots tested 10 6 = conversion to parts per million (ppm) reliability data analysis reliability is the probability that a semiconductor device will perform its specified function in a given environment for a specified period. in other words, reliability is quality over time and environmental conditions. the most frequently used reliability measure for semiconductor devices is the failure rate ( l ). the failure rate is obtained by dividing the number of failures observed by the product of the number of devices on test and the interval in hours, usually expressed as percent per thousand hours or failures per billion device hours (fits). this is called a point estimate because it is obtained from observations on a portion (sample) of the population of devices. to project from the sample to the population in general, one must establish confidence intervals. the application of confidence intervals is a statement of how ``confident'' one is that the sample failure rate approximates that for the population. to obtain failure rates at different confidence levels, it is necessary to make use of specific probability distributions. the chisquare ( c 2) distribution that relates observed and expected frequencies of an event is frequently used to establish confidence intervals. the relationship between failure rate and the chisquare distribution is as follows: l = c 2 ( a , d. f.) 2t where: l = failure rate c 2 = chisquare function a = (100 confidence level) / 100 d.f. = degrees of freedom = 2r + 2 r = number of failures t = device hours chisquare values for 60% and 90% confidence intervals for up to 12 failures are shown in table 11. table 11 chisquare table chisquare distribution function 60% confidence level 90% confidence level no. fails c 2 quantity no. fails c 2 quantity 0 1 2 3 4 5 6 7 8 9 10 11 12 1.833 4.045 6.211 8.351 10.473 12.584 14.685 16.780 18.868 20.951 23.031 25.106 27.179 0 1 2 3 4 5 6 7 8 9 10 11 12 4.605 7.779 10.645 13.362 15.987 18.549 21.064 23.542 25.989 28.412 30.813 33.196 35.563 the failure rate of semiconductor devices is inherently low. as a result, the industry uses a technique called accelerated testing to assess the reliability of semiconductors. during accelerated tests, elevated stresses are used to produce, in a short period, the same failure mechanisms as would be observed under normal use conditions. the objective of this testing is to identify these failure mechanisms and eliminate them as a cause of failure during the useful life of the product. temperature, relative humidity, and voltage are the most frequently used stresses during accelerated testing. their relationship to failure rates has been shown to follow an eyring type of equation of the form: l = a exp( f kt) w exp(b/rh) w exp(ce) where a, b, c, f , and k are constants, more specifically b, c, and f are numbers representing the apparent energy at which various failure mechanisms occur. these are called activation energies. ``t'' is the temperature, ``rh'' is the relative humidity, and ``e'' is the electric field. the most familiar form of this equation (shown on following page) deals with the first exponential term that shows an arrhenius type relationship of the failure rate versus the junction temperature of semiconductors. the junction temperature is related to the ambient temperature through the thermal resistance and power dissipation. thus, we can test devices near their maximum junction temperatures, analyze the failures to assure that they are the types that are accelerated by temperature and then by applying known acceleration factors, estimate the failure rates for lower junction. the table on the following page shows observed activation energies with references.
913 reliability and quality assurance motorola smallsignal transistors, fets and diodes device data table 12 time dependent failure mechanisms in semiconductor devices (applicable to discrete and integrated circuits) device association process relevant factors accelerating factors typical activation energy in ev model reference silicon oxide siliconsilicon oxide interface metallization bond and other mechanical interfaces various water fab, assembly, and silicon defects surface charges inversion, accumulation oxide pinholes dielectric breakdown (tddb) charge loss electromigration corrosion chemical galvanic electrolytic intermetallic growth metal scratches mask defects, etc. silicon defects mobile ions e/v, t e/v, t e/v, t e, t t, j grain size doping contamination t, impurities bond strength t, v t, v e, t e, t e, t j, t h, e/v, t t t, v 1.0 0.71.0 (bipolar) 1.0 (bipolar) 0.30.4 (mos) 0.3 (mos) 0.8 (mos) eprom 1.0 large grain al (glassivated) 0.5 small grain al 0.7 cual/cusial (sputtered) 0.60.7 (for electrolysis) e/v may have thresholds 1.0 (au/al) 0.50.7 ev 0.5 ev fitch, et al. peck 1984 wrs hokari, et al. domangue, et al. crook, d.l. gear, g. nanda, et al. black, j.r. black, j.r. lycoudes, n.e. fitch, w.t howes, et al. mmpd 1a 2 18 5 3 4 11 6 7 12 8 9 10 13 v = voltage; e = electric field; t = temperature; j = current density; h = humidity no. reference 1a 1.0 ev activation for leakage type failures. fitch, w.t.; greer, p.; lycoudes, n.; ``data to support 0.001%/1000 hours for plastic i/c's.'' case study on linear product shows 0.914 ev activation energy which is within experimental error of 0.9 to 1.3 ev activation energies for reversible leakage (inversion) failures reported in the literature. 1b 0.7 to 1.0 ev for oxide defect failures for bipolar structures. this is under investigation subsequent to information obtained from 1984 wafer reliability symposium, especially for bipolar capacitors with silicon nitride as dielectric. 2 1.0 ev activation for leakage type failures. peck, d.s.; ``new concerns about integrated circuit reliability'' 1978 reliability physics symposium. 3 0.36 ev for dielectric breakdown for mos gate structures. domangue, e.; rivera, r.; shedard, c.; ``reliability prediction using large mos capacitors'', 1984 reliability physics symposium. 4 0.3 ev for dielectric breakdown. crook, d.l.; ``method of determining reliability screens for time dependent dielectric breakdown'', 1979 reliability physics symposium. 5 1.0 ev for dielectric breakdown. hokari, y.; et al.; iedm technical digest, 1982. 6 1.0 ev for large grain alsi (compared to line width). nanda, vangard, gjp; black, j.r.; ``electromigration of alsi alloy films'', 1978 reliability physics symposium. 7 0.5 ev al, 0.7 ev cual small grain (compared to line width). black, j.r.; ``current limitation of thin film conductor'' 1982 reli- ability physics symposium. 8 0.65 ev for corrosion mechanism. lycoudes, n.e.; ``the reliability of plastic microcircuits in moist environments'', 1978 solid state technology. 9 1.0 ev for open wires or high resistance bonds at the pad bond due to aual intermetallics. fitch, w.t.; ``operating life vs junction temperatures for plastic encapsulated i/c (1.5 mil au wire)'', unpublished report. 10 0.7 ev for assembly related defects. howes, m.g.; morgan, d.v.; ``reliability and degradation, semi- conductor devices and circuits'' john wiley and sons, 1981. 11 gear, g.; ``famous prom reliability studies'', 1976 reliability physics symposium. 12 black, j.r.: unpublished report. 13 motorola memory products division; unpublished report.
reliability and quality assurance 914 motorola smallsignal transistors, fets and diodes device data thermal resistance circuit performance and longterm circuit reliabiity are affected by die temperature. normally, both are improved by keeping the junction temperatures low. electrical power dissipated in any semiconductor device is a source of heat. this heat source increases the temperature of the die about some reference point, normally the ambient temperature of 25 5 c in still air. the temperature increase, then, depends on the amount of power dissipated in the circuit and on the net thermal resistance between the heat source and the reference point. the temperature at the junction depends on the packaging and mounting system's ability to remove heat generated in the circuit from the junction region to the ambient environment. the basic formula for converting power dissipation to estimated junction temperature is: t j = t a + p d ( q jc + q ca ) (1) or t j = t a + p d ( q ja ) (2) where: t j = maximum junction temperature t a = maximum ambient temperature p d = calculated maximum power dissipation, including effects of external loads when applicable q jc = average thermal resistance, junction to case q ca = average thermal resistance, case to ambient q ja = average thermal resistance, junction to ambient this motorola recommended formula has been approved by radc and desc for calculating a ``practical'' maximum operating junction temperature for milm38510 devices. only two terms on the right side of equation (1) can be varied by the user, the ambient temperature and the device casetoambient thermal resistance, q ca . (to some extent the device power dissipation can also be controlled, but under recommended use the supply voltage and loading dictate a fixed power dissipation.) both system air flow and the package mounting technique affect the q ca thermal resistance term. q jc is essentially independent of air flow and external mounting method, but is sensitive to package material, die bonding method, and die area. for applications where the case is held at essentially a fixed temperature by mounting on a large or temperature controlled heat sink, the estimated junction temperature is calculated by: t j = t c + p d ( q jc ) (3) where t c = maximum case temperature and the other parameters are as previously defined. air flow air flow over the packages (due to a decrease in q jc ) reduces the thermal resistance of the package, therefore permitting a corresponding increase in power dissipation without exceeding the maximum permissible operating junction temperature. for thermal resistance values for specific packages, see the motorola data book or design manual for the appropriate device family or contact your local motorola sales office. activation energy determination of activation energies is accomplished by testing randomly selected samples from the same population at various stress levels and comparing failure rates due to the same failure mechanism. the activation energy is represented by the slope of the curve relating to the natural logarithm of the failure rate to the various stress levels. in calculating failure rates, the comprehensive method is to use the specific activation energy for each failure mechanism applicable to the technology and circuit under consideration. a common alternative method is to use a single activation energy value for the ``expected'' failure mechanism(s) with the lowest activation energy.
915 reliability and quality assurance motorola smallsignal transistors, fets and diodes device data reliability stress tests the following are brief descriptions of the reliability tests commonly used in the reliability monitoring program. not all of the tests listed are performed by each product division. other tests may be performed when appropriate. autoclave (aka, pressure cooker) autoclave is an environmental test which measures device resistance to moisture penetration and the resultant effect of galvanic corrosion. autoclave is a highly accelerated and destructive test. typical test conditions : t a = 121 5 c, rh = 100%, p = 1 atmosphere (15 psig), t = 24 to 96 hours common failure modes : parametric shifts, high leak- age and/or catastrophic common failure mechanisms : die corrosion or con- taminants such as foreign material on or within the pack- age materials. poor package sealing. high humidity high temperature bias (h3tb, h3trb, or thb) this is an environmental test designed to measure the moisture resistance of plastic encapsulated devices. a bias is applied to create an electrolytic cell necessary to accelerate corrosion of the die metallization. with time, this is a catastrophically destructive test. typical test conditions : t a = 85 5 c to 95 5 c, rh = 85% to 95%, bias = 80% to 100% of data book max. rating, t = 96 to 1750 hours common failure modes : parametric shifts, high leak- age and/or catastrophic common failure mechanisms : die corrosion or con- taminants such as foreign material on or within the pack- age materials. poor package sealing. high temperature gate bias (htgb) this test is designed to electrically stress the gate oxide under a bias condition at high temperature. typical test conditions : t a = 150 5 c, bias = 80% of data book max. rating, t = 120 to 1000 hours common failure modes : parametric shifts in gate leak- age and gate threshold voltage common failure mechanisms : random oxide defects and ionic contamination military reference : milstd750, method 1042 high temperature reverse bias (htrb) the purpose of this test is to align mobile ions by means of temperature and voltage stress to form a highcurrent leakage path between two or more junctions. typical test conditions : t a = 85 5 c to 150 5 c, bias = 80% to 100% of data book max. rating, t = 120 to 1000 hours common failure modes : parametric shifts in leakage and gain common failure mechanisms : ionic contamination on the surface or under the metallization of the die military reference : milstd750, method 1039 high temperature storage life (htsl) high temperature storage life testing is performed to accelerate failure mechanisms which are thermally activated through the application of extreme temperatures typical test conditions : t a = 70 5 c to 200 5 c, no bias, t = 24 to 2500 hours common failure modes : parametric shifts in leakage and gain common failure mechanisms : bulk die and diffusion defects military reference : milstd750, method 1032 intermittent operating life (iol) the purpose of this test is the same as ssol in addition to checking the integrity of both wire and die bonds by means of thermal stressing typical test conditions : t a = 25 5 c, pd = data book maximum rating, t on = t off = of 50 5 c to 100 5 c, t = 42 to 30000 cycles common failure modes : parametric shifts and cata- strophic common failure mechanisms : foreign material, crack and bulk die defects, metallization, wire and die bond defects military reference : milstd750, method 1037
reliability and quality assurance 916 motorola smallsignal transistors, fets and diodes device data mechanical shock this test is used to determine the ability of the device to withstand a sudden change in mechanical stress due to abrupt changes in motion as seen in handling, transportation, or actual use. typical test conditions : acceleration = 1500 g's, orienta- tion = x 1 , y 1 , y 2 plane, t = 0.5 msec, blows = 5 common failure modes : open, short, excessive leak- age, mechanical failure common failure mechanisms : die and wire bonds, cracked die, package defects military reference : milstd750, method 2015 moisture resistance the purpose of this test is to evaluate the moisture resistance of components under temperature/humidity conditions typical of tropical environments. typical test conditions : t a = 10 5 c to 65 5 c, rh = 80% to 98%, t = 24 hours/cycles, cycle = 10 common failure modes : parametric shifts in leakage and mechanical failure common failure mechanisms : corrosion or contami- nants on or within the package materials. poor package sealing military reference : milstd750, method 1021 solderability the purpose of this test is to measure the ability of the device leads/terminals to be soldered after an extended period of storage (shelf life). typical test conditions : steam aging = 8 hours, flux = r, solder = sn60, sn63 common failure modes : pin holes, dewetting, nonwet- ting common failure mechanisms : poor plating, contami- nated leads military reference : milstd750, method 2026 solder heat this test is used to measure the ability of a device to withstand the temperatures as may be seen in wave soldering operations. electrical testing is the endpoint critierion for this stress. typical test conditions : solder temperature = 260 5 c, t = 10 seconds common failure modes : parameter shifts, mechanical failure common failure mechanisms : poor package design military reference : milstd750, method 2031 steady state operating life (ssol) the purpose of this test is to evaluate the bulk stability of the die and to generate defects resulting from manufacturing aberrations that are manifested as time and stressdependent failures. typical test conditions : t a = 25 5 c, p d = data book maximum rating, t = 16 to 1000 hours common failure modes : parametric shifts and cata- strophic common failure mechanisms : foreign material, crack die, bulk die, metallization, wire and die bond defects military reference : milstd750, method 1026 temperature cycling (air to air) the purpose of this test is to evaluate the ability of the device to withstand both exposure to extreme temperatures and transitions between temperature extremes. this testing will also expose excessive thermal mismatch between materials. typical test conditions : t a = 65 5 c to 200 5 c, cycle = 10 to 4000 common failure modes : parametric shifts and cata- strophic common failure mechanisms : wire bond, cracked or lifted die and package failure military reference : milstd750, method 1051 thermal shock (liquid to liquid) the purpose of this test is to evaluate the ability of the device to withstand both exposure to extreme temperatures and sudden transitions between temperature extremes. this testing will also expose excessive thermal mismatch between materials. typical test conditions : t a = 0 5 c to 100 5 c, cycle = 20 to 300 common failure modes : parametric shifts and cata- strophic common failure mechanisms : wire bond, cracked or lifted die and package failure military reference : milstd750, method 1056 variable frequency vibration this test is used to examine the ability of the device to withstand deterioration due to mechanical resonance. typical test conditions : peak acceleration = 20 g's, frequency range = 20 hz to khz, t = 48 minutes common failure modes : open, short, excessive leak- age, mechanical failure common failure mechanisms : die and wire bonds, cracked die, package defects military reference : milstd750, method 2056
917 reliability and quality assurance motorola smallsignal transistors, fets and diodes device data statistical process control communication power & signal technologies group (cpstg) is continually pursuing new ways to improve product quality. initial design improvement is one method that can be used to produce a superior product. equally important to outgoing product quality is the ability to produce product that consistently conforms to specification. process variability is the basic enemy of semiconductor manufacturing since it leads to product variability. used in all phases of motorola's product manufacturing, statistical process control (spc) replaces variability with predictability. the traditional philosophy in the semiconductor industry has been adherence to the data sheet specification. using spc methods ensures that the product will meet specific process requirements throughout the manufacturing cycle. the emphasis is on defect prevention, not detection. predictability through spc methods requires the manufacturing culture to focus on constant and permanent improvements. usually, these improvements cannot be bought with stateoftheart equipment or automated factories. with quality in design, process, and material selection, coupled with manufacturing predictability, motorola can produce world class products. the immediate effect of spc manufacturing is predictability through process controls. product centered and distributed well within the product specification benefits motorola with fewer rejects, improved yields, and lower cost. the direct benefit to motorola's customers includes better incoming quality levels, less inspection time, and shiptostock capability. circuit performance is often dependent on the cumulative effect of component variability. tightly controlled component distributions give the customer greater circuit predictability. many customers are also converting to justintime (jit) delivery programs. these programs require improvements in cycle time and yield predictability achievable only through spc techniques. the benefit derived from spc helps the manufacturer meet the customer's expectations of higher quality and lower cost product. ultimately, motorola will have six sigma capability on all products. this means parametric distributions will be centered within the specification limits, with a product distribution of plus or minus six sigma about mean. six sigma capability, shown graphically in figure 1, details the benefit in terms of yield and outgoing quality levels. this compares a centered distribution versus a 1.5 sigma worst case distribution shift. new product development at motorola requires more robust design features that make them less sensitive to minor variations in processing. these features make the implementation of spc much easier. a complete commitment to spc is present throughout motorola. all managers, engineers, production operators, supervisors, and maintenance personnel have received multiple training courses on spc techniques. manufacturing has identified 22 wafer processing and 8 assembly steps considered critical to the processing of semiconductor products. processes controlled by spc methods that have shown significant improvement are in the diffusion, photolithography, and metallization areas. figure 1. aoql and yield from a normal distribution of product with 6 s capability standard deviations from mean distribution centered distribution shifted + 1.5 at + 3 s 2700 ppm defective 99.73% yield at + 4 s 63 ppm defective 99.9937% yield at + 5 s 0.57 ppm defective 99.999943% yield at + 6 s 0.002 ppm defective 99.9999998% yield 66810 ppm defective 93.32% yield 6210 ppm defective 99.379% yield 233 ppm defective 99.9767% yield 3.4 ppm defective 99.99966% yield 6 s 5 s 4 s 3 s 2 s 1 s 01 s 2 s 3 s 4 s 5 s 6 s to better understand spc principles, brief explanations have been provided. these cover process capability, implementation, and use. process capability one goal of spc is to ensure a process is capable . process capability is the measurement of a process to produce products consistently to specification requirements. the purpose of a process capability study is to separate the inherent random variability from assignable causes . once completed, steps are taken to identify and eliminate the most significant assignable causes. random variability is generally present in the system and does not fluctuate. sometimes, the random variability is due to basic limitations associated with the machinery, materials, personnel skills, or manufacturing methods. assignable cause inconsistencies relate to time variations in yield, performance, or reliability. traditionally, assignable causes appear to be random due to the lack of close examination or analysis. figure 2 shows the impact on predictability that assignable cause can have. figure 3 shows the difference between process control and process capability. a process capability study involves taking periodic samples from the process under controlled conditions. the performance characteristics of these samples are charted against time. in time, assignable causes can be identified and engineered out. careful documentation of the process is the key to accurate diagnosis and successful removal of the assignable causes. sometimes, the assignable causes will remain unclear, requiring prolonged experimentation. elements which measure process variation control and capability are cp and cpk, respectively. cp is the specification width divided by the process width or cp = (specification width) / 6 s . cpk is the absolute value of the closest specification value to the mean, minus the mean, divided by half the process width or cpk = h closest specification x /3 s .
reliability and quality assurance 918 motorola smallsignal transistors, fets and diodes device data figure 2. impact of assignable causes on process predictable figure 3. difference between process control and process capability ? ? ? ? ? ? ? ? ? process aunder controlo all assignable causes are removed and future distribution is predictable. prediction time size size time prediction size time out of control (assignable causes present) in control assignable causes eliminated size time in control but not capable (variation from random variability excessive) lower specification limit upper specification limit in control and capable (variation from random variability reduced) ? ? at motorola, for critical parameters, the process capability is acceptable with a cpk = 1.50 with continual improvement our goal. the desired process capability is a cpk = 2 and the ideal is a cpk = 5. cpk, by definition, shows where the current production process fits with relationship to the specification limits. off center distributions or excessive process variability will result in less than optimum conditions. spc implementation and use cpstg uses many parameters that show conformance to specification. some parameters are sensitive to process variations while others remain constant for a given product line. often, specific parameters are influenced when changes to other parameters occur. it is both impractical and unnecessary to monitor all parameters using spc methods. only critical parameters that are sensitive to process variability are chosen for spc monitoring. the process steps affecting these critical parameters must be identified as well. it is equally important to find a measurement in these process steps that correlates with product performance. this measurement is called a critical process parameter. once the critical process parameters are selected, a sample plan must be determined. the samples used for measurement are organized into rational subgroups of approximately two to five pieces. the subgroup size should be such that variation among the samples within the subgroup remain small. all samples must come from the same source e.g., the same mold press operator, etc. subgroup data should be collected at appropriate time intervals to detect variations in the process. as the process begins to show improved stability, the interval may be increased. the data collected must be carefully documented and maintained for later correlation. examples of common documentation entries are operator, machine, time, settings, product type, etc. once the plan is established, data collection may begin. the data collected with generate x and r values that are plotted with respect to time. x refers to the mean of the values within a given subgroup, while r is the range or greatest value minus least value. when approximately 20 or more x and r values have been generated, the average of these values is computed as follows: x = (x + x 2 + x 3 + . . .)/k r = (r1 + r2 + r2 + . . .)/k where k = the number of subgroups measured. the values of x and r are used to create the process control chart. control charts are the primary spc tool used to signal a problem. shown in figure 4, process control charts show x and r values with respect to time and concerning reference to upper and lower control limit values. control limits are computed as follows: r upper control limit = ucl r = d4 r r lower control limit = lcl r = d3 r x upper control limit = ucl x = x + a2 r x lower control limit = lcl x = x a2 r
919 reliability and quality assurance motorola smallsignal transistors, fets and diodes device data 147 148 149 150 151 152 153 154 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 0 1 2 3 4 5 6 7 ucl = 152.8 = 150.4 lcl = 148.0 ucl = 7.3 = 3.2 lcl = 0 x r figure 4. example of process control chart showing oven temperature data where d4, d3, and a2 are constants varying by sample size, with values for sample sizes from 2 to 10 shown in the following partial table: n2345678910 d 4 3.27 2.57 2.28 2.11 2.00 1.92 1.86 1.82 1.78 d 3 * * * * * 0.08 0.14 0.18 0.22 a 2 1.88 1.02 0.73 0.58 0.48 0.42 0.37 0.34 0.31 *for sample sizes below 7, the lcl r would technically be a negative number; in those cases there is no lower control limit; this means that for a subgroup size 6, six ``identical'' measurements would not be unreasonable. control charts are used to monitor the variability of critical process parameters. the r chart shows basic problems with piece to piece variability related to the process. the x chart can often identify changes in people, machines, methods, etc. the source of the variability can be difficult to find and may require experimental design techniques to identify assignable causes. some general rules have been established to help determine when a process is outofcontrol . figure 5 shows a control chart subdivided into zones a, b, and c corresponding to 3 sigma, 2 sigma, and 1 sigma limits respectively. in figures 6 through 9 four of the tests that can be used to identify excessive variability and the presence of assignable causes are shown. as familiarity with a given process increases, more subtle tests may be employed successfully. once the variability is identified, the cause of the variability must be determined. normally, only a few factors have a significant impact on the total variability of the process. the importance of correctly identifying these factors is stressed in the following example. suppose a process variability depends on the variance of five factors a, b, c, d, and e. each has a variance of 5, 3, 2, 1, and 0.4, respectively. since: s tot = s a 2 + s b 2 + s c 2 + s d 2 + s e 2 s tot = 5 2 + 3 2 + 2 2 + 1 2 +(0.4) 2 = 6.3 if only d is identified and eliminated, then: s tot = 5 2 + 3 2 + 2 2 + (0.4) 2 = 6.2 this results in less than 2% total variability improvement. if b, c, and d were eliminated, then: s tot = 5 2 + (0.4) 2 = 5.02 this gives a considerably better improvement of 23%. if only a is identified and reduced from 5 to 2, then: s tot = 2 2 + 3 2 + 2 2 + 1 2 + (0.4) 2 = 4.3 identifying and improving the variability from 5 to 2 yields a total variability improvement of nearly 40%. most techniques may be employed to identify the primary assignable cause(s). outofcontrol conditions may be correlated to documented process changes. the product may be analyzed in detail using best versus worst part comparisons or product analysis lab equipment. multivariance analysis can be used to determine the family of variation (positional, critical, or temporal). lastly, experiments may be run to test theoretical or factorial analysis. whatever method is used, assignable causes must be identified and eliminated in the most expeditious manner possible. after assignable causes have been eliminated, new control limits are calculated to provide a more challenging variablility criteria for the process. as yields and variability improve, it may become more difficult to detect improvements because they become much smaller. when all assignable causes have been eliminated and the points remain within control limits for 25 groups, the process is said to in a state of control.
reliability and quality assurance 920 motorola smallsignal transistors, fets and diodes device data ucl lcl ucl ucl ucl ucl lcl lcl lcl lcl centerline a b c c b a a b c c b a a b c c b a a b c c b a zone a (+ 3 sigma) zone b (+ 2 sigma) zone c (+ 1 sigma) zone c ( 1 sigma) zone b ( 2 sigma) zone a ( 3 sigma) figure 5. control chart zones figure 6. one point outside control limit indicating excessive variability figure 7. two out of three points in zone a or beyond indicating excessive variability figure 8. four out of five points in zone b or beyond indicating excessive variability figure 9. seven out of eight points in zone c or beyond indicating excessive variability summary motorola is committed to the use of statistical process controls. these principles, used throughout manufacturing have already resulted in many significant improvements to the processes. continued dedication to the spc culture will allow motorola to reach the six sigma and zero defect capability goals. spc will further enhance the commitment to total customer satisfaction .
device replacement device replacement device replacement replacement devices replacement devices 102 motorola smallsignal transistors, fets and diodes device data 1n5139 mv2101 1n5139a mv2101 1n5140 mmbv2103lt1 1n5140a mmbv2103lt1 1n5141 mmbv2104lt1 1n5141a mmbv2104lt1 1n5142 mmbv2105lt1 1n5142a mmbv2105lt1 1n5143 mmbv2105lt1 1n5143a mmbv2105lt1 1n5144 mmbv2107lt1 1n5144a mmbv2107lt1 1n5145 mmbv2108lt1 1n5145a mmbv2108lt1 1n5146 mmbv2109lt1 1n5146a mv2109 1n5147 mv2111 1n5147a mv2111 1n5441a mv2101 1n5443a mv2103 1n5444a mv2104 1n5445a mv2105 1n5449a mv2108 1n5450a mv2109 1n5451a mv2111 1n5452a mv2111 1n5453a mv2111 1n5455a mv2115 2n697 mpsa20 2n718a mpsa05 2n720a mpsa06 2n930 mpsa18 2n930a mpsa18 2n956 mpsa05 2n1613 2n4410 2n1711 mpsa05 2n1893 mpsa06 2n2102 2n4410 2n2218a mps2222a 2n2219 mps2222a 2n2219a mps2222a 2n2222 mps2222 2n2222a mps2222a 2n2270 mpsa05 2n2369 mps2369 2n2369a mps2369a 2n2484 2n5087 2n2895 mpsa06 2n2896 2n5551 2n2904 mps2907 2n2904a mps2907a 2n2905 mps2907 2n2905a mps2907a 2n2906 mps2907 2n2906a mps2907a 2n2907 mps2907 2n2907a mps2907a 2n3019 mpsa06 2n3020 mpsa06 2n3053 mpsa20 2n3053a mpsa05 2n3244 2n4403 2n3250 2n4403 2n3251 mps2907a 2n3251a mps2907a 2n3467 mpsa56 2n3468 mpsa56 2n3497 2n5401 2n3500 2n5551 2n3501 2n5551 2n3546 mpsh17 2n3634 2n5401 2n3635 2n5401 2n3636 mpsa92 2n3637 mpsa92 2n3700 mpsa06 2n3799 mpsa18 2n3947 mps2222a 2n3963 mpsa18 2n3964 mpsa18 2n4014 mps2222a 2n4032 mps2907a 2n4033 mpsa56 2n4036 mpsa56 2n4037 mpsa56 2n4126 mps4126 2n4265 2n4264 2n4405 mps8599 2n4407 mps8599 2n4931 mpsa92 2n5086 2n5087 2n5668 2n3819 2n5669 2n3819 2n5670 2n3819 2n6431 mpsa42 2n6433 mpsa92 2n6516 2n6517 ba582t1 mmbv3401lt1 bc107 bc237 bc107a bc237 bc107b bc237 bc108 bc109c bc3338 bc14010 mpsw06 bc14016 mpsw06 bc14110 mpsw06 bc14116 mpsw06 bc16016 mpsw56 bc16116 mpsw56 bc177 bc547 bc177a bc547a bc177b bc547b bc238 bc238b bc309b bc308c bc393 mpsa92 bc394 mpsa42 bc450 mpsa92 bc450a mpsa92 bc546a bc546b bc559 bc559b bc560b bc560c bc849alt1 bc848alt1 bc850alt1 bc848alt1 bc857clt1 bc857alt1 bcy70 mps2222a bcy71 mps2222a bcy72 mps2222a bdb01d bdb01c bdb02d bdb02c bdc02d bdc01d bdc05 mpsw42 bf244a 2n3819 bf244b 2n3819 bf245 bf245a bf245a bf245a bf245b bf245a bf245c bf245a bf246a bf245a bf246b bf245a bf247b bf245a bf256b bf256a bf256c bf256a bf258 bf422 bf374 bc338 bf391 mpsa42 bf392 mpsa42 bf492 mpsa92 bf493 mpsa92 bfw43 2n5401 bsp20at1 bf720t1 bss71 mpsa42 bss72 mpsa42 bss73 mpsa42 bss74 mpsa92 bss75 mpsa92 bss76 mpsa92 bss89 bs107 bsv1610 mps2907a bsx20 mps2369a cv12253 mpsa06 irfd110 bss123lt1 irfd113 mmbf170lt1 irfd120 bss123lt1 irfd123 mmbf170lt1 irfd210 mmft107t1 irfd213 mmft107t1 irfd220 mmft107t1 irfd223 mmft107t1 irfd9120 bss123lt1 irfd9123 2n7002lt1 j111 j111rlra j113 j113rl1 j203 2n5458 j300 2n5486 j305 mmbf5484lt1 mad130p bas16lt1 mad1103p bas16lt1 mad1107p bas16lt1 mad1108p bas16lt1 mad1109p bas16lt1
device replacement device replacement device replacement replacement devices 103 replacement devices motorola smallsignal transistors, fets and diodes device data mm3001 2n5551 mm3725 mps2222a mm4001 2n5401 mmad1106 bas16lt1 mmbf4856lt1 mmbf4391lt1 mmbf4860lt1 mmbf5457lt1 mmbf5459lt1 mmbf5457lt1 mmbf5486lt1 2n5486 mmbt8599lt1 mmbt5551lt1 mmbv2104lt1 mmbv2103lt1 mmpq3799 mmpq3725 mmsv3401t1 mmbv3401lt1 mpf970 mmbfj175lt1 mpf971 mmbfj175lt1 mpf3821 mmbf5457lt1 mpf3822 mmbf5457lt1 mpf4856 mpf4391rlra mpf4857 2n5639 mpf4858 j112 mpf4859 2n5638rlra mpf4860 2n5638rlra mpf4861 j112 mpq6501 mpq6502 mps3638 mps3638a mps3866 bf224 mps4123 mps4124 mps4125 mps4126 mps4258 mps3640 mps5771 mps3640 mps6520 mps6521 mps6530 mps6530rlrm mps6531 mps6530rlrm mps6562 mps6651 mps6568a mps918 mps6571 mpsa18 mps6595 mps3563 mps8093 2n4402 mpsa16 mpsa17 mpsh04 mpsh17 mpsh07a mpsh17 mpsh20 mpsh17 mpsh24 mpsh17 mpsh34 mpsh17 mpsh69 mpsh81 msa1022bt1 msa1022ct1 msb709st1 msb709rt1 msb710qt1 msb710rt1 msb1218ast1 msb1218art1 msc1621t1 msd602rt1 msc2404ct1 msc2295ct1 msd1819ast1 msd1819art1 mv1620 mv2101 mv1624 mmbv2103lt1 mv1636 mv2108 mv1640 mv2109 mv1642 mv2111 mv1644 mv2111 mv2103 mmbv2103lt1 mv2107 mv2108 mv2113 mv2111 mv2114 mv2115 mvam108 mmbv2109lt1 mvam109 mmbv2109lt1 mvam115 mmbv2109lt1 mvam125 mmbv2109lt1 pbf259 mmbt6517lt1 pbf259s mmbt6517lt1 pbf259rs mmbt6517lt1 pbf493 mmbta92lt1 pbf493r mmbta92lt1 pbf493rs mmbta92lt1 pbf493s mmbta92lt1 vn1706l mmft107t1

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